Technical meeting for Hardware Engineers

Submitted by shahnaz on Wed, Nov 11 2009 - 11:14 AM

Our last meeting was a success and I would like to see the same level of energy & interactions in future discussions.
The next meeting is scheduled for Wednesday, November 18th at the DBM location on Great Hills from 10AM - noon. I am looking for Engineers to present at the meeting. Below are examples of topics that can be discussed.

Clock distribution, skew, jitter
Analog design & Mixed signal design
LSSD & MUXD designs
SOI vs BULK
Parasitic Extraction
Cache related Arch Questions
System verilog
Power measurements, IR & EM
Process variation
Static & Dynamic circuit designs
Layout & DFM
Latch/Flop designs ..
.. add your topics here

So if you are interested in presenting, please send me (shahnaz.nagle@gmail.com) your topic & name by Friday. It will be good to have 2-3 presenters per meeting.

Thanks,
Shahnaz

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Comments

Sounds great! Please feel

Submitted by matt on Mon, Nov 16 2009 - 12:45 AM.

Sounds great! Please feel free to keep posting your talks on the door64 calendar. There's lot of chip folks on here who are probably interested in participating.

Thanks, I am planning to

Submitted by shahnaz on Mon, Nov 16 2009 - 2:42 PM.

Thanks, I am planning to host this study group weekly. I would like to encourage Engineers to attend and then present their areas when they feel comfortable. This meeting can be used as a platform for technical interview practice.