Physical Synthesis: the Good, the Bad, and the Ugly

Location: Building ENS (Engineering and Science) 306A on UT Campus

http://maps.google.com/maps/ms?hl=en&ie=UTF8&msa=0&msid=1088379744524717...

This event is one of the monthly seminar series hosted by IEEE Central Texas Solid-State Circuits / Circuits and Systems Joint Chapter.

Cost: free
Refreshments: Cookies, soft drink

Abstract:
A decade ago, physical synthesis emerged as a design aid to address the problem of optimization after cell placement caused by increasingly high wire delays. Early physical synthesis tools were fairly simplistic scripts wrapped around traditional placement and logic synthesis optimizations. Advances and technology have put increasing pressure on physical synthesis tools not only to perform timing takedown with increasingly aggressive frequences but also to manage many additional design constraints like power management, routability, and variability. Trying to solve all aspects of physical implementation simultaneously creates massive complexity for both the tool and the designer.

This talk overviews the basics of physical synthesis, from placement to buffering to gate sizings and explains fundamentally how a physical synthesis flow weaves together its components to perform timing closure. It explains how the complexity of physical synthesis and corresponding designs have mushroomed to create design problems that are not just bad, but sometimes downright ugly.

Biography:
Charles (Chuck) Alpert received two undergraduate degrees from Stanford University in 1991 and his doctorate from UCLA in 1996 in Computer Science. Upon graduation, Chuck joined IBM's Austin Research Laboratory where he remains still. He currently manages the Design Productivity Group, whose mission is to architect design automation tools and methodologies to improve designer productivity and reduce design cost. Chuck is the proud husband to his wife Cheryl and their three girls Candice, Ciara, and Charlie.

Chuck has published over 100 conference and journal papers and has thrice received the Best Paper Award from the ACM/IEEE Design Automation Conference. He has been active in the academic community, serving as chair for the Tau Workshop on Timing Issues and the International Symposium on Physical Design. He also serves as an associate editor of IEEE Transactions on Computer-Aided Design. For his work in mentoring, he received the Mahboob Khan Mentor Award in 2001 and 2007. He was also named IEEE Fellow in 2005.