IEEE SSC/CAS July meeting: Bridging Design and Manufacture of Analog/Mixed-Signal Circuits in Advanced CMOS

Please register here: https://meetings.vtools.ieee.org/meeting_view/list_meeting/13097

Topic: Bridging Design and Manufacture of Analog/Mixed-Signal Circuits in Advanced CMOS

ABSTRACT
This tutorial-oriented seminar will be an extended encore of a paper presented at the 2011 IEEE Symposium on VLSI Technology in Kyoto, Japan. We present device and circuit characterization resulting from technology/design co-development to improve the design and manufacture of analog/mixed-signal circuits in processors. We introduce ID-based MOSFET transconductance measurements and a new measurement of drain saturation margin at realistic analog biasing. We also describe routinely monitored scribe lane replicas of key analog/mixed-signal passive devices and circuits. Such measurements enable construction and validation of compact models better suited to analog/mixed-signal needs than those historically tailored for logic design. Finally, we will cover new analog design enhancements in HSPICE resulting from co-development work with Synopsys.

BIOGRAPHY OF SPEAKER
Alvin Loke received the BASc degree from the University of British Columbia and the MSEE and PhDEE degrees from Stanford University. From 1998 to 2001, he worked on CMOS technology integration at HP Labs (Palo Alto, CA) and then at Chartered Semiconductor Manufacturing (Singapore) as an Agilent assignee. In 2001, he transferred to Fort Collins, CO, where he designed CMOS phase-locked loop circuits for low-jitter embedded SerDes I/O and ASIC core clocking. In 2006, he joined Advanced Micro Devices where he is currently a Principal Member of Technical Staff designing high-speed links and interfacing with technology teams on analog/mixed-signal concerns. Dr. Loke has authored 38 publications and holds 12 US patents. He presently serves on the CICC technical program committee and IEEE Solid-State Circuits Society (SSCS) Chapters committee. He is presently the SSCS Webinar Taskforce Chair, a Guest Editor for the IEEE Journal of Solid-State Circuits, and an IEEE Distinguished Lecturer.

Location: ENS 314 (UT Campus Engineering Science Bldg.)
ENS is in Section 4 of map found at: http://www.utexas.edu/maps/
Occasionally you might find street level parking for free -- but watch out for the parking signs and restrictions. Another place to park is SJG, the San Jacinto Garage (Section 6) -- after 6PM, it is $7 to park all night.