IEEE CEDA August Inaugural meeting: Design Automation Conference 2012 Review
Venue: Freescale @ Parmer
Link for details and for registration:
No Cost. BBQ and drink will be provided.
06:00 to 06:15 pm networking time
06:15 to 06:45 pm Introduction to CEDA Chapter and DAC 2012 general review by Zhuo Li
06:45 to 07:15 pm POWER Processor Design and Methodology Directions (one of the DAC Keynotes) by Joshua Friedrich
07:15 to 07:45 pm Overview of Accellera Systems Initiative and IEEE Design Technology Committee by Bill Read
07:45 to 08:00 pm DAC 2013 (50th DAC) in Austin and Q&A
Joshua Friedrich of IBM
Topic: POWER Processor Design and Methodology Directions
Processor designs and the EDA tools that support them stand at a key inflection point. The era of Dennard scaling and exponential single thread performance growth is a distant memory. Multi-thread performance continues to grow. However, the gain from simply adding more cores to a die by stepping to the next process node is diminishing due to technology challenges, application bottlenecks, and power/packaging constraints. To continue to deliver the cost-performance gains that drive our industry, designers will need to bring significant innovation to bear by integrating heterogeneous system components and accelerating key portions of the software stack in hardware. This transformation from technology-driven design to innovation-driven design defines new priorities for EDA development compared to prior eras. While timing optimization, power reduction, and support for modular designs remain necessary, differentiation will be achieved by enabling designer productivity through technology simplification, design abstraction, and robust support for heterogeneous IP.
Biography: Joshua Friedrich is a Senior Technical Staff Member and Senior Manager of POWERTM Technology Development in IBM’s Server and Technology Group. In his role, Josh leads the physical design, technology direction, and methodology of IBM’s future POWERTMprocessors. Josh has been part of the POWER development team since POWER4TM, and on past POWERTM designs, Josh has led multiple design disciplines including power estimation and reduction, hardware characterization, memory subsystem circuit development, and core execution units. Before joining IBM, Josh received his Bachelor of Science in Electrical Engineering from the University of Texas at Austin.
Topic: Overview of Accellera Systems Initiative and IEEE Design Technology Committee
Accellera Systems Initiative (ASI) – Overview of ASI, current activities/standards and future directions. IEEE Design Technology Committee (DTC) - Overview of the DTC and current activities.
Biography: Over 30 years experience in research and development of EDA tools, methodologies, flows and standards. Currently, a Distinguished Member of Technical Staff in the Design Technology organization within Freescale Semiconductor, Vice Chair of the SRC CAD & Test science area coordinating committee, Chair of the IEEE Design Technology Committee and on the Board of Directors of Accellera Systems Initiative. Previously worked in CAD departments at AT&T Bell Laboratories and MCC. Received a PhD in Electrical Engineering from the University of Texas at Austin.