GRAPE-DR Project: A combination of peta-scale computing and high-speed networking

Computer Architecture Seminar Series (http://www.cs.utexas.edu/users/cart/arch)

Speaker: Kei Hiraki, University of Tokyo
Place: ACES 2.402
Host: Derek Chiou

Abstract:

The University of Tokyo and the National observatory of Japan have been jointly developing a GRAPE-DR system, which realize a combination of Peta-Scale computing and very high-speed data-sharing system for scientific computing. In this talk, we describe the outline of GRAPE-DR project, architecture of the GRAPE-DR processor, and the methods used in Data-Reservoir system which is used to share data among distant research institutes.

Main objectives of GRAPE-DR system are (1) realization of very cost-effective and power-efficient computation, (2) construction of a practical peta-scale computing system for computation-intensive scientific applications. GRAPE-DR adopts different approach, SIMD architecture without interconnects between processing elements(PEs). Figure 1 shows block diagram of GRAPE-DR processor chip. All the data transfer to and from PEs are achieved by broadcasting memory and reduction network with arithmetic units. This architecture is effective to reduce the amount of hardware. As shown in Table 1, the size of the die is much smaller than other chips for HPC systems, such as nVIDIA 8800 or CELL.

GRAPE-DR chip is carefully designed to compute several important applications including n-body problem for galaxy generation, molecular dynamics, quantum molecular simulation (e.g. FMO), dense linear equations (e.g. Linpack), and simulation in bio-informatics.