ASIC Verification Engineer
Our group is responsible for creating several cluster testbenches for advanced Ethernet controllers that combine networking, storage, and high performance computing functionality at 10/40Gb speeds. These testbenches are implemented using the Specman `e' language with OVM. As part of the pre-silicon Architectural Validation (AV) team you'll help develop test plans from architecture and design specifications, design testbenches, write tests, gather and analyze coverage results, plug coverage holes, and debug problems in the design and AV environment.
Bachelor or Master Electrical Engineering or Computer Engineering
3 years of experience in ASIC Verification
3 or more years of OVM and/or VMM
3 or more years of experience with Verilog
3 or more years of experience with simulation debugging
Additional Preferred Qualifications:
-Experience with designing functional coverage driven test benches written in Specman `e' using eRM (eRe-use Methodology.
-Knowledge of the following is a plus: Ethernet, TCP/IP, any protocols running on top of TCP, digital logic simulation, C++.
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