Certified Project Management Professional

Timothy J. Ehrler, PMP

7613 Jaborandi Dr., Austin, TX 78739
Phone: 512-382-6764 - Cell: 623-680-1551
http://www.linkedin.com/in/timothyehrler
tehrler@austin.rr.com

CERTIFIED PROJECT MANAGEMENT PROFESSIONAL

PROFESSIONAL PROFILE

Corporate level certified project manager with extensive engineering, management, and liaison/interface expertise among senior management, technology partners and alliances, and industry coalitions, enabled through excellent organizational, leadership, decision making, interpersonal, and communication skills. Proven initiative, innovation, and expertise in architecture and development of software applications, semiconductor design methodologies, and database engineering, demonstrated through patented accomplishments, industry coalition leadership, and conference presentations and panel discussions.

KEY SKILLS and COMPETENCIES

* Project management with emphasis on high-quality, on-time product delivery
* Experience establishing PMO-equivalent project management policies, processes, and procedures
* Corporate engineering liaison expertise among technology partners and industry alliances
* Management of international and domestic multiple-site task, group, and project teams
* Inter-organizational group and process interface, integration, and consolidation leadership
* Architect level software engineering and management expertise with object-oriented development skills demonstrated through applied CMMI processes, industry recognition, and awarded patents
* Extensive background in management and implementation aspects of semiconductor design methodology for SoC, ASIC, uP/GPU designs, including EDA/CAD software development and project management
* Proactive participation and chairmanship in IEEE and global industry coalitions and standards committees with leadership in strategic adoption, implementation, and integration across engineering environments

PROFESSIONAL EXPERIENCE

Advanced Micro Devices (AMD), Austin, TX - 2006 to 2008

Senior Manager, CAD Global Infrastructure (2006-2008)
Second-level project manager of three engineering teams comprising 25 engineers responsible for definition, planning, and development of design methodologies and tools, providing infrastructure in support of design environments for high-speed and low-power microprocessor designs, with emphasis on high-quality, on-time software application/tool development and support.
* Managed the planning, implementation, and delivery of a relative-placement tool for 45nm node semiconductor designs after assuming management of troubled, nonviable project efforts
* Introduced and drove software quality improvement and maturity initiatives for code quality, change management, and metrics collection/analysis targeting software and project planning improvement
* Managed the development and support of design data management and distribution systems for globally located, multiple-site design centers
* Provided common physical design kit (PDK) supporting Cadence design tools and Analog Design Environment, including migration from vendor-specific CDB design database to industry-standard OpenAccess design database that enabled corporate-wide design interoperability in support of design tools for advanced 32nm technology compute and graphic processor designs

Principal Member Technical Staff (2006)
Technical staff position providing leadership and guidance for the evolution and quality improvement of semiconductor EDA design flows and software applications/tools.
* Initiated efforts that successfully standardized in-house standard cell library development and generation processes and deliverables
* Audited design flows and identified areas of required design data interoperability for methodology convergence and industry-standard design database migration

Philips Semiconductors, Tempe AZ (formerly VLSI Technology) - 1993 to 2006

ASIC Technical Program Manager (2001-2006)
Executive technical staff position responsible for definition, requirements, planning, development, and management of IP-based semiconductor design environment architecture, methodology, software applications, and task flows throughout design process, including infrastructure management & support, technology-specific characterization, design flows, and corresponding software applications development.
* Managed project development and implementation for unique, ground-breaking development of persistent timing constraints within industry-standard OpenAccess design database
* Architected and managed implementation of the Chip Physical Architecture domain of the 90nm CMOS SoC Design Environment concerning areas of hierarchical partitioning and chip assembly, including development of corresponding task flows, tools, and user documentation
* Lead role for adoption of OpenAccess across design environments, providing consultation, guidance, and formal project management that enabled improved tool & task interoperability and IP reuse targeting 65nm CMOS technology
* Coordinated efforts between Philips technology groups, Crolles Alliance (Philips, Freescale, and STMicroelectronics), and EDA vendors to ensure OpenAccess availability and interoperability consistent with process technology and standard cell library objectives

Manager ASIC Tool Software Development (1997-2001)
Managed 12 member team responsible for software application development, maintenance, and support of proprietary EDA tools for ASIC developers concerning characterization, model/view generation, and timing analysis within the VLSI Technology Design Integrator design flow.
* Technical liaison and primary application provider between VLSI and Hitachi Semiconductors supporting design flow, methodology, and EDA tools, in support of technology exchange agreement
* Project lead for re-architecture of VLSI design flows to Philips Semiconductors design environment as VLSI/Philips integration task force member
* Project lead for Advanced Library Format (ALF) characterization database requirements definition and support, with subsequent project leadership for design environment re-architecture and migration from Compass Design Automation to ALF characterization based design system
* Lead role in definition, planning, development, and support of Open Library Architecture (OLA) application procedural interface and required corresponding design library content within Philips in coordination with process and library technology groups

Manager Model Technology Software Development (1996-1997)
Managed 5 member team responsible for software application development, maintenance, and support of proprietary EDA tools for ASIC developers pertaining to model generation and memory compilers within the VLSI Technology Design Integrator design flow.
* Project management and implementation lead for integrated model and library generation applications, and for the integrated memory compiler, including 3rd party EDA tool and application library interface and support of generated models and libraries

Staff Software Engineer (1993-1996)
Leadership role for software application development, maintenance, and support of model/view generation and memory compilers for VLSI Technology design kits supporting internal and external customers and design centers.

FORMAL EDUCATION
Bachelor of Science, Computer and Information Science, College of Engineering, The Ohio State University

PROFESSIONAL DEVELOPMENT
PMP Certification Training
Business Creation and Management: Process Management
CMU/SEI Capability Maturity Model (CMM)
CMU/SEI CMM Integration (CMMI): Staged & Continuous
Architect level software engineering with object-oriented C/C++ programming and scripting skills
Eclipse IDE and ClearCase configuration management knowledge and experience
EDA tools and applications - Cadence Design Systems, Synopsys, Mentor Graphics, proprietary
Business and productivity software - Microsoft Office (Word, Excel, PowerPoint, Project, Visio, Outlook), OpenOffice, IBM Lotus Notes

CERTIFICATIONS / AFFILIATIONS / PROFESSIONAL ORGANIZATIONS
PMP Certification (Project Management Professional) - Project Management Institute
IEEE member since 1996 - DASC, DASC Steering Committee, DASC Standards Association
* IEEE 1481v2 (2008) - DCL/DPCM version 2 revision & ballot activities
* IEEE 1481 with extensions - Open Library Architecture (OLA)
* IEEE 1603 - Accellera Advanced Library Format (ALF)
* IEEE P24765 - Standard for Systems and Software Engineering - Vocabulary
* IEEE P1175.5 - Standard for Computer-Aided Software Engineering (CASE) Tool Interconnections: Reference Data Metamodel for System Behavior Specifications
Industry coalition participation under Silicon Integration Initiative (Si2)
* Open Modeling Coalition - coalition chair, Technical Steering Board, Architecture Work Group, chair Joint Data Model Work Group w/OAC
* OpenAccess Coalition - Change Team, Golden Gate Bridge, chair Timing Work Group

PATENTS / AWARDS
US Patent #7,010,475 (software), "Derating Factor Determination for Integrated Circuit Logic Design Tools", March 7, 2006 (Philips Semiconductors innovation award)
US Patent #6,038,384 (software), "Input Slope Timing Analysis and Non-Linear Delay Table Optimization", March 14, 2000 (VLSI Technology, Inc., publication and innovation awards)
Silicon Integration Initiative (SI2) Special Recognition Award for "Outstanding Open Library Architecture (OLA) Development Efforts"
Bull Worldwide Information Systems Technical Excellence Award for the "Enhancement of the Design Language System and Integration with Groupe Bull Design Automation Tools"

PUBLICATIONS / PRESENTATIONS / PANELS
Session chair for "Open Modeling", 12th OpenAccess+ Conference 2008
Panel session chair for "Low Power Design", 9th OpenAccess+ Conference 2006
"Open Modeling Coalition Strategy", 8th OpenAccess Conference 2006
"Philips Semiconductors OpenAccess Migration", DesignCon 2006
"Open Library Access thru Standard Data Interface Architecture", 7th OpenAccess Conference 2005
"Into the Depths of OpenAccess: Timing Constraints Implementation", 6th OpenAccess Conference 2005
"Non-Linear Delay Table Optimization of Input Slope Timing Models", Synopsys Users Group 1996
Technical panel discussion member at DAC 2004 Interoperability Workshop, DATE (2005, 2004 - session chair, 2001), DesignCon (2006, 2004), ICCAD 2003, CICC 2001