Combining Circuits + Architecture to Combat Variability in Nanoscale CMOS

Event: UT VLSI Seminar Series
http://www.cerc.utexas.edu/vlsi-seminar/

Speaker: Gu-Yeon Wei, Harvard University

Date: Tuesday, January 22, 2008
Time: 5:00 pm
Place: ACES 2.302
Coffee: 4:30 pm
Host: Steve Keckler

ABSTRACT:

Variability is poised to severely degrade performance and power scalability of circuits and systems in nanoscale CMOS technologies. Process, voltage, and temperature variations are well-known effects that occur across wide temporal and spatial scales. With aggressive technology scaling, traditional worst-case design techniques incur too much overhead. Higher-level solutions, combined with innovations at the circuit level, offer a holistic approach that should combat and mitigate the detrimental effects of variability. This talk presents a broad perspective of how circuits and architecture can be combined to address varibility in different contexts.

Random and systematic variation can introduce skew between clock phases in a high-speed interleaved transmitter. Instead of applying circuit-level patches, we treat offsets as a form of internal inter-symbol interference (ISI) and show how a look-up table (LUT) based equalizer can compensate internal clock timing and transmitter current mismatch to improve signal integrity. In addition to mixed-signal transceiver blocks, process variation can degrade power and performance of digital systems. We investigate two techniques to combat variability---voltage interpolation and variable latency---applied to a 6-stage floating-point unit (FPU). Experimental results from a 130nm FPU test chip demonstrate how these techniques can compensate for random and correlated device-level variations without compromising performance. Besides process variation, voltage variation can also degrade performance scalability and incur large power overheads. Hence, we investigate the potential for energy savings offered by temporally fine-grained, per-core DVFS using integrated on-chip switching regulators. Our analysis suggests energy savings are possible through fast, per-core DVFS despite the overheads associated with lower-efficiency on-chip regulators.