Result oriented fellow, with one & half year of academic experience in Digital Integrated circuit design

Nishit Shah
712 SW 16th Avenue, Apt#215
Gainesville, FL-32601
(281) 678-4163
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EDUCATION:

Master’s of Science in Electrical and Computer Engineering
GPA 3.56 May 2010
UNIVERSITY OF FLORIDA
Gainesville, Florida,USA

Bachelor of Engineering in Electronics and Communication Engineering
CGPA 3.82 May 2008
GUJARAT UNIVERSITY
Gujarat, India
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TECHNICAL SKILLS:

•Full Custom Transistor level IC Design using Cadence design suite.
•Physical design using cadence and synopsys compiler.
•RTL design using Xilinx ISE and mentor graphics
•FPGA design.
•Circuit simulation and analysis using Agilent ADS, Specter, LT-Spice, spectre, NC-Sim, Multisim.
•Programming skills – VHDL/Verilog/C/Perl.
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RELAVANT COURSES:

•Advanced VLSI Circuits, MOS Analog IC Design, Microwave IC Design, RF Circuits, Computer Architecture, Embedded Sys.
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PROFESSIONAL EXPERIENCE:

Edutech Systems
Intern, Embedded Design Group
•Designed Board Support Package (BSP) for MSP430, an Ultra low power microcontroller from Texas Instruments.
•Board Support Package included Application Program Interface (APIs) for various On-Chip peripherals like SPI, USART, I2C, DMA Controller, LCD Controller and Off-Chip peripherals like graphical LCD.
•Designed an application of Radio Frequency Identification (RFID) based attendance monitoring system, on MSP430.
•Designed with High level language C.
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PROJECTS:

•Ultra-low power ECoG (ElectroCorticoGraphic activity) Processor:(Full custom IC design)
--Full-Custom design (0.25µm) of ECoG Processor in which Electrocorticographic activity recorded from cortical surface of brain serves as modality for non-invasive BCI (Brain Computer Interface).
--Its basic architecture consists of FFT processor (8-point 16-bit Butterfly algorithm), digital band-pass filters (FIR Filter) and a squaring circuit. Band pass filters are used to segregate three band of frequency recorded from brain surface. After filtering, time-domain signal is converted to frequency domain signal with FFT processor and power Spectrum was estimated using squaring circuit.
--Sub-threshold CMOS logic was implemented for ultra-low power consumption. Final power dissipation was about 0.122µW

•Dynamic Scheduling of Pipelined processor using Tomasulo Algorithm: (MIPS Architecture Optimization)
--Optimized 5-stage MIPS pipeline with dynamically scheduling the Instructions with out-of-order Execution and in-order commit.
--Out-of-order Execution was accomplished with the help of register renaming to eliminate the potential hazards, while in-order commit was achieved by implementation of Re-order Buffer.

•Assembler and Pipelined Instruction Set Simulator (MIPS Architecture Implementation)
--Developed an assembler for custom Instruction Set Architecture, which translates assembly code to a machine language.
--Developed the 5-stage pipelined Instruction Set Simulator that will process the binary instruction through the pipeline and give the correct output. Challenge was to implement pipeline while considering various hazards and branching conditions.

•Vending Machine Controller using Place and Route: (ASIC design)
--Basic idea of Vending Machine Controller was to dispense the soda when correct amount is inserted in it or to dispense soda and change when extra amount was inserted it. It consisted of two basic entities, Controller and Arithmetic Logic Unit (ALU).
--Designed in VHDL using Xilinx-ISE. Controller was realized using Finite State Machine while ALU was combinational entity.
--Gate level net-list was synthesized using Synopsys Design Compiler while Placement and Routing was done using Cadence Encounter

•Design and Layout of SRAM: (Memory design)
--Full-Custom design of 6-T, SRAM using TSMC 0.25µm technology. Involved design of address decoders, sense amplifier, precharge circuitry, write circuitry.
--Distinguishing feature of the design was clocked CMOS Latched sense amplifier for reduced power consumption and reasonable read access time. Cadence Virtuoso was used to design layout of the design.

•FPGA Implementation of Steganography: (FPGA Design)
--Project involved development and implementation of hardware architecture for private key Steganography on Xilinx FPGA.
--Secret message was encoded and hidden into the cover image by replacing several bits of cover image at random address.
--Successfully encoded and decoded the image and text, into and from the image. Developed in Xilinx ISE.

•Gigabit WLAN Transceiver system design: (RF System design)
--Designed Gigabit WLAN Ethernet system, operating at 60 GHz RF, QPSK modulated with wide bandwidth of 500 MHz.
--Implemented low-IF (5 GHz) transceiver architecture resulting in high level of integration on-chip.
--Achieved 1Gbps bitrate covering range of 10m.