Modeling and Performance Analysis of Computer Architecture

Freescale Semiconductors (May 2005 – August 2007)

Performance Analysis of PowerPC Processors

The work included enhancement and verification of cycle accurate simulator for e500 PowerPC core. It involved working with benchmarks like SPEC CPU 2000, and developing methods for debugging simulator failures for such multi-billion instruction-long benchmarks. I did performance evaluation studies for several architectural configurations for processors and SoCs, working with instruction traces, benchmarks and performance simulators using various performance projection methodologies. I also worked with EEMBC benchmarks, investigating the effects of different compiler flags for different compilers, for a variety of platforms. I enhanced an instruction trace collection tool to support new architecture extensions. I also participated in efforts for workload characterization based on several static and dynamic parameters.

Profile

I am looking for an internship position for the summer of 2008. I am currently pursuing PhD in Computer Science in University of California, Irvine. My interests are in performance analysis and modeling of heterogeneous multi-core and single-core systems. Previously, I have worked in Freescale Semiconductors in performance analysis of PowerPC cores and energy model for Starcore VLIW DSP processor. I have also worked in ST Microelectronics and developed signal processing modules and codecs for 3G wireless cellular networks. I have done my M.Tech [Masters in Technology] from Indian Institute of Technology [IIT], Bombay in Electronic Systems, with a focus on embedded system design and signal processing. I want to work in system performance analysis and power / performance / temperature modeling for single-core and multi-core systems or a related area.