Mixed Signal Designer

Sanjay Patil

11004 Pebble Garden Ln., Austin, TX 78739
Cell: (512) 731-2781/573-1063
sanjay_97@yahoo.com

OBJECTIVE
Seeking Mixed Signal IC Design Position Focused On Low Power.

CORE COMPETENCY
Device Physics, Transistor Fundamentals, CMOS Custom Circuit Design, CMOS Low Power Designs and Methodologies, ASIC Design, Analog Design, IO, ROM/SRAM, NanoSim/UltraSim, IR Drop Analysis, Clock Tree/Bus Modeling.

EXPERIENCE
Freescale Inc., Austin, Texas
Low Power Circuit Design Engineer June 2005 - May 2008
Conceived and worked on various aspects of multiple State Retention Power Gating (SRPG) and Power Gating (PG) schemes to substantially reduce (1000x) device off leakages for cmos90, cmos65 and cmos45 nodes for wireless products.
SPRG power saving techniques ranged from employing simple hvt sleep device as a switch to more advanced gate and well biasing switch leakage reduction schemes.
Custom designed (Cadence/Spice) distributed sleep transistor library cells, SRPG flops, voltage references, and analog switch controllers to smoothly power up internal cores/blocks.
Duties included optimization and integration of switches along with analog controllers to deliver Active/SCAN functional currents (UltraSim) while maintaining area, off leakages, switch IR drop and power up performance tradeoffs.
Simulated and analyzed internal power grid IR drop dynamics (ElixIR/VoltageStorm) during power up, worst case active and scan conditions to assure crucial state retention.

Design Engineer Dec. 1998 – June 2005
Designed 0.13u high speed DDR1 SSTL2 IO for StarLite product.
Besides IO circuit design, other tasks included were defining functional/electrical IO specifications, performing pad limit analysis and devising optimal pad placement methodology for common package and backward footprint compatibility across all StarLite devices, C4/WB package evaluation and selection tradeoffs in terms of cost, IO performance, power delivery, thermal ratings and package features .
Designed chip power grid for a WB package to meet IR drop budgets, derived Active/SCAN current signatures (NanoSim) for DC/AC IR drop simulations (ElixIR), decoupling caps (MIMs) analysis to meet AC current demands, signal integrity analysis (PrimeTime-SI/ClariNet), chip power analysis, dynamic and static timing analysis (NanoSim, PrimeTime).
Prior to this, custom designed DSP platform bus that integrates core with various top level modules.
Defined specs for DSP’ Enhanced On Chip Emulator (EOnCE), wrote functional assembly test vectors, performed RTL synthesis using Design Compiler.

DCTC, Motorola Inc., Gurgaon, New Delhi, India
Design Manager, IDC (Expatriate) Jan. 1998 – Dec. 1998
Relocated to India as an expatriate to help start India Design Center at Gurgaon.
Recruited experienced engineers as well as fresh graduates on a large scale from various regions of country and via campus interviews, respectively.
Trained new personnel with 16 bit DSP design methodologies, design flows and in-house tools.
Led DSP56825 as a first pilot project.
Dealt with typical challenges of startup such as, HR, hardware/software licences procurement, workstations, IT, UNIX networking, setting satellite link, office space planning, office cultural transformation and dealing with government regulations.

DSP Division, Motorola Inc., Austin, Texas
Senior DSP Design Engineer Jan. 1993 – Dec. 1997
Was involved in over half a dozen 16 bit DSP56100/56800 chips/derivatives tape-outs. The duties included work on entire chip design flow.
Understanding existing and designing new DSP architectures, module definitions (Program Decoder, Program Interrupt Controller, External Memory Port, Internal Bus Interface Unit, ROMs/RAMs, Flash Memory), defining module specs, behavioral coding (Verilog/M Models), defining signal timings, module integration (Cadence/GDT), writing production test vectors (Verilog XL/Lsim/ATPG).
Implementing these modules by designing full custom (datapath) and synthesized (control logic) low power high-speed CMOS digital circuits. This involved RTL coding and synthesis (Synopsys/AutoLogic), schematic capture (Composer/Led) and spicing full custom datapath for optimal speed, power and area (McSpice/PowerMill).
Block and chip level static (PathMill/CPF) and dynamic (TimeMill/VTRAN) critical path analysis and transistor level functional verification (Verilog).
Other duties included block/die size estimation and floor planning, P&R (Gards), extracting parasitic for back annotation (CheckMate), clock/bus modeling, data sheets timing, ROM code generation, electro-migration, LVS, DRC, antenna rule verification, participate in technical reviews, instructing layout designer, documenting completed designs for future reference (Maker), characterize and debug final silicon product in laboratory using E-Beam and probe tester, bug fixing and customer support.

Naval Command, Control and Ocean Surveillance Center (NOSC), San Diego, California
Analog Circuit Designer Dec. 1991 – Dec. 1992
Designed CMOS analog building blocks such as current mirrors, voltage references, comparators, OpAmps, current conveyors, resistor string, decoders and control circuitry.
Nonvolatile Floating Gate Memory Cell design for analog signal processing applications.
Duties included transistor level circuit design, schematic capture (NetEd), HSpice simulations and logic simulations, layout (Led), DRC, LVS, and silicon testing and evaluation on a probe station and parametric analyzer HP4145.

Siemens Electronics Ltd., Bombay, India
Design Engineer July 1987 – Dec. 1989
Designed medical electronics equipment, CNC controls, PLC, board level design etc. Assisted in setting up test facility.

EDUCATION
M.S., Electrical and Computer Engineering, Oklahoma State University, Stillwater, Oklahoma 1991
Thesis: Hardware implementation of Neural Networks involving NVM element as a synaptic element
Major: Digital/Analog VLSI Engineering; DSP, Digital VLSI Systems, Adv. Digital VLSI Systems, CMOS Analog IC Design, Adv. CMOS System IC, Digital System Testing.

B.S., College of Engineering, University of Poona, Poona, India, India 1987
First Class with Distinction

B.S., EE, Govt. Polytechnic College, Yeotmal, India 1984
State Rank Holder

AWARDS
Recipient of Gold Award; DSP division, Motorola: DSP56811 ATPG functional verification
Patents and Publications: 4 publications in VLSI circuit design.

Immigration Status
US Citizen