Computer Architecture and Embedded Processors Research Review

2nd Annual Computer Architecture and Embedded Processors Research Review for Industry
August 26, 2008
Avaya Auditorium (Room 2.302 ACES Bldg)

9:00 am Welcome Professor Yale Patt
9:10 am Keynote: Transforming Computer System Design - Professor Derek Chiou
10:00 am Break
10:30 am Embedded Real-Time Signal Processing Systems - Professor Brian L. Evans
11:00 am Fast Power Estimation of Computers - Dam Sunwoo (D. Chiou)
11:20 am Dynamic Power Management on Multi-Core Processors - Lloyd Bircher (L. John)
11:40 am On the Representativeness of Embedded Java Benchmarks - Ciji Isen (L. John)

12:00 pm Lunch

1:00 pm Prefetch-Aware DRAM Controller: How to control prefetch and demand
requests for high performance - Chang Joo Lee (Y. Patt)
1:20 pm An Asymmetric Multi-core Architecture for Accelerating Critical
Sections in Multi-threaded Workloads - Aater Suleman (Y. Patt)
1:40 pm Application Specific Processing - Professor Earl Swartzlander
2:10 pm Hardware/Software Co-simulation of Real-time Embedded Systems - Professor Jonathan Valvano

2:40 pm Break

3:10 pm High-Level Programming, Design and Modeling of Embedded
Multi-Processor Systems - Professor Andreas Gerstlauer
3:40 pm CMPs and NoCs with Fast Global Communication - Ikhwan Lee (M. Erez)
4:10 pm Reducing the Cost of Last-Level Cache ECC - Doe Hyun Yoon (M. Erez)

4:30 pm Closing remarks

Register online at http://www.ece.utexas.edu/news/research-review-2008/.

For more information, please contact Leticia Lira at 512-471-4662 or email
her at letylira@mail.utexas.edu.