Cadence Low Power Workshop in Austin

Product battery life, system packaging considerations, advanced process node migration and new environmental guidelines are requiring designers, for the first time, to consider incorporating power reduction circuitry and techniques into their systems and chips. As one research study concluded, every watt saved in the chip results in 3 watts of savings in the system. Yet, designers are reluctant to design in advanced low-power techniques due to the risk of silicon failure, time to market pressures, and/or performance trade-offs. Can designs be made power efficient yet be able to meet performance targets, conform to original schedule, and enjoy a risk-free tapeout?

The Cadence® Low-Power Solution has helped many companies achieve their project goals by helping them incorporate low-power design techniques without sacrificing performance while reducing costs and mitigating both schedule and chip functionality/quality risks. This production-proven solution has enabled customers to deliver first time silicon using the most advanced low-power design techniques.

Join us to learn how Cadence and other major companies in the Power Forward Initiative (PFI) are taking an innovative approach to successfully solving this rising critical customer challenge. Listen to some of the industry's top experts in the field of low power.

Register today for the September 3rd workshop in Austin! Limited availability:

http://www.secure-register.net/cadence/lowpower_techtorials

WHO SHOULD ATTEND?
* Design managers and engineers
* Verification managers and engineers
* Implementation managers and engineers
* System architects, executives and design chain providers
* Anyone who is interested in low-power technologies and methodologies

What you will learn:

Explore your teams' options for managing power throughout the entire design process, receive methodology recommendations based on proven silicon success, and learn how you can effectively deploy those methodologies in your design environment today - risk free.

Agenda:

8:30 – 9:00 Registration and Continental Breakfast
9:00 – 9:30 Cadence Low-Power Solution Overview
9:30 – 10:00 Partner Presentation – ARM
10:00 – 10:45 Customer Presentation
10:45 – 11:00 Break
11:00 – 11:30 Partner Presentation – Si2
11:30 – 12:00 Panel Discussion/Q&A
12:00 – 1:00 Lunch/Cadence Low-Power Solution Demo
1:00 – 5:00 Hands-on Workshops (Space is limited, registration available on first-come basis)