SystemVerilog User Group Meeting

In addition to the presentations by industry experts during the user group meetings, we are also offering 2 tutorials. These tutorials will take place before the meeting in the same location and last about 90 minutes. Both start at the same time so you have to pick one or the other. They will be repeated at every SVUG meeting so if you don't have a chance to attend, there is always next time.

The goal is simple. If you are just starting to look at SystemVerilog, then the 'Fundamentals of SystemVerilog' is something you should not miss. This is a short introduction to the IEEE 1800-2005 SystemVerilog RTL and behavioral design enhancements to increase design and coding efficiency. The only prerequisite is previous experience with Verilog or VHDL. The second tutorial is a concise tour of the verification features of SystemVerilog. Prior knowledge of verification and Verilog will be helpful to get the most out of this tutorial.

Location: Cool River Cafe (North Austin)

For agenda, registration, see: http://www.svug.org/Events/SVUGAustin/tabid/93/Default.aspx