Computer Design in the Nanometer Scale Era: Challenges and Solutions

Computer Architecture Seminar Series
http://www.cs.utexas.edu/users/cart/arch

Speaker: David Brooks, Harvard

Date: Monday, September 8, 2008
Time: 3:30 pm
Place: ACES 2.402 (UT)
Coffee: 3:00 pm
Host: Steve Keckler

ABSTRACT:
Technology scaling has enabled tremendous growth in the computing industry over the past few decades. However, recent trends in power dissipation, reliability, thermal constraints, and device variability threaten to limit the continued benefits of device scaling, curtail performance improvements, and cause increased leakage power in future technology generations. The temporal and spatial scales of these effects motivate holistic solutions that span the circuit, architecture, and software layers. In this talk, I will describe several ongoing projects that seek to address technology scaling issues. These projects include efforts in the areas of a) power and performance modeling and design space optimization for future chip-multiprocessor systems, b) variability-tolerant design of memory hierarchies, and c) accelerator-based architectures for power/performance efficiency. The talk will also discuss our chip prototyping efforts that support this work.