ASIC designer

PROFESSIONAL EXPERIENCE
2006 - 2007
IBM - Austin, TX
Electronic Design Automation (EDA) Engineer
Methodology owner of newly released(2006) ASIC netlist based power estimation tool, PSS_PowerEval. Applied knowledge of ASIC design flow, libraries, Tcl, and XML in working closely with Power Team and customers to improve capability and quality in power estimation. Coordinated and negotiated feature releases with other tools to ensure coherence and stability of the tool suite. Triage reported problems to prioritize or re-assign to appropriate owners.
* Added a FET width calculator to estimate leakage power.
* Assured functionality for early use in new technologies.
* Drove updates to library power models to assure accurate estimates within PSS_PowerEval.
* Implemented usability for netlist Sign Off to manufacturing.

2004 - 2006
XEMI Inc. - Austin, TX
Digital Design Engineer
Architect, design and verify a clock decoder front end for a PLL used in a
zero delay clock buffer chip. Interfaced with Synopsys Design Services to
place & route, extract parasitics, verify timing, using STA and mixed-mode
simulations. Devise and conduct tests to qualify, characterize devices.
* Designed a glitch free clock decoder using standard cells.
* Developed lab automation system for a 4x speed up in data collection for
characterization and failure analysis.

2004
Intel Corporation - Hillsboro, OR
Temp/Contract as Physical Design Engineer
Maintained and improved Synopsys PrimeTime(PT) Tcl scripts for full chip and block level timing analysis.
* Eliminated errors by scripting transfer of inter clock skew and jitter from Excel spreadsheet to the PT Tcl scripts.

1993 - 2003
Hewlett-Packard (formerly Compaq and Tandem) - Austin, TX
Senior Hardware Engineer
Led geographically dispersed team of five to deliver gate level netlist to the chosen ASIC vendor. Synthesized, verified timing, and generated test vectors for ASICs used for memory interfaces and bus conversion in fault tolerant computers. Selected and managed ASIC vendors.
* Completed design with over 80 clock domains on-time and under budget.
* Designated as expert to advise other engineers on Design-For-Test (DFT) and test vector issues because of extensive experience and knowledge.
* Contributed to design productivity increases of 5X while product complexity increased by 20X during a five-year time span.
* Designed eight complex ASICs within ten years, none of which required respin.
* Increased team's productivity and shortened time to synthesize by advancing process improvements.
* Successfully released designs to IBM, LSI, AMI, and Toshiba.
* Synthesized verilog code for Altera FPGA to overcome timing problems because of predetermined pinout and multiple clocks.
* Achieved test vector coverage in high nineties for all ASIC designs.