Senior Mask Design Specialist

JAMES COSTABILE
Senior IC Layout Design Specialist
2402 Hunters Creek Cove, Cedar Park, TX 78613-5906
512-336-8688, mobile 954-815-9350
texas4ever@netscape.com

QUALIFICATIONS:
25+ years experience in IC Layout Design. Proficient in Analog, Digital, CMOS, BiCMOS, design processes. Experienced in RFIC and Mixed Signal designs. Outstanding history of fast, clean, tight, and on-time designs.

TOOLS:
Design - Cadence Virtuoso, Cadence Edge, Cadence Fasttrack, Cadence Opus, Cadence LayoutXL, IC Craftsman (VCR), Silicon Ensemble, STX, Mentor Cell Station, Mentor Chipgraph, Sun Forum, Tridia VNC.
Verification - Diva, Dracula, Vampire, Assura, Avant!, Hercules Explorer, Calibre.

EXPERIENCE:
Contract Work [2002 - Present]
Integrated Device Technology, Inc, Austin, TX
Contract Senior Mask Designer
Project Komodo, analog/digital design, RFIC, Mixed Signal,CEMOS 11.5 process.
Responsible for layout and verification (Cadence and Hercules tools) of various
complex designs.
Work closely with Design Engineer on various design strategies; keep re-work
to a minimum.
Plan and layout entire wiring of chip.
Revise and edit schematics.
Designs include: decoders, bias generators, stereo amps, ref vaggen, stereo
headphone capless amp, differential amp, vbat and hundreds more.

Qualcomm, La Jolla, CA
Contract Senior Mask Designer
Project PMIC4, analog and digital design, RFIC, Mixed Signal, chrt18 process
Responsible for layout and verification (Cadence, and Calibre tools) of various
designs using a new process for Temp. monitor.
temp_dac_res_string, temp_iptat_amp2, alarm_dac_amp, temp_ipat_res
Re-design, reduce, and verify over 350 Standard digital cells.
Re-design and edit 5 verification documents.
Re-design and verify custom digital blocks.

Freescale Semiconductor, Boca Raton, FL
Contract Senior Mask Designer
Project Kaibab, cmos90 process, analog and digital design
Responsible for layout and verification (Cadence, Assura, and Calibre tools) of
various designs from the cell level to top level block.
Revise schematics as needed.
Routing for top level blocks
Work closely with Design Engineers.
Trouble shoot pre-existing layout.
bias ctrl, vref, ramp, comp, feedback, amp, ilimit, ovdd ctrl, isource bias, dac tune,
isteer, atm1, atm2, testswitch, steer ctrl, buffer, lshifter 1p2to1p5, regulator 1p8v,
regulator 1p5v, regulator 1p2v, pre bias, rf top, imux

Silicon Labs, Austin, TX
Contract Senior Mask Designer
Create new RF design cells for an existing project. Design and layout large DAC
block.
Design and layout Offload Dac and other corner circuitry with probe points.
Re-wire portions of existing chip.
Layout and verify vbat op-amp.

Motorola Labs, Plantation, FL
Contract Senior Mask Designer
Design entire DPA test chip using IBM 8HP process.
Layout utilizing Cadence Virtuoso 5.0 LayoutXL and Assura for verification with
IBM’s checking script.
Interface with IBM Foundry on verification issues.
Instrumental in finding bugs in their checking deck.
Design and verify bias gen, buffers, inductors, mixers, various inverter cells, diff amp
drivers, tgates, and various other cells.
Chip taped out on time even with a 6 week starting delay.
Create detailed document to teach Engineers how to layout and verify cells.
Kept ongoing status report of chip design progress.
Edit existing instructions on how to send a tar version of design verification issues to
the IBM Foundry for de-bugging.
Create a test chip using cmos90 analog process. Design and verify input buffer, diff
amp, mixers, muxes, vco, and many more designs utilizing Cadence 5.0 Virtuoso,
LayoutXL, and Assura checking tool.

Freescale Semiconductor - Plantation, FL
Contract Senior Mask Designer
Assist Project Leader with floor planning a re-design of an existing chip using a new
Analog technology.
Design and verify buffers, filters, and timing blocks using Cadence Virtuoso 5.0 and
Assura checking tool.

Intersil - Dallas, TX
Contract Senior Mask Designer
Help staff with floor planning of high voltage BiCMOS analog chip.
Layout macro blocks, op amp, bias macro, and trim macro. Hookup wiring of entire
chip.
Design utilizing Cadence Fasttrack, verification DIVA.
Contract was for 5 weeks, brought in tape out date to 2.5 weeks.

Intel - Chandler, AZ
Contract Senior Mask Designer
Layout digital SRAM bit cell, muxbit cells, rfmbit cells, decoders, control blocks,
I/O’s, drivers, word line mux, read mux, and word line latch, analog op amps, buffers,
level shifters, and A/D converters.
Use matching and common centroid design techniques. Utilized Cadence Opus 5.0,
LayoutXL. Verification using Explorer.

Cypress Semiconductor - Austin, TX [2000 - 2001]
Staff Layout Engineer
Design and layout CMOS and BiCMOS analog flash memory macro blocks, I/O
buffers, A/D converters, op amps, and clock circuitry. Create new type of inductor
cell.
Verified designs using Vampire checking tool. Coordinated design flow between
Austin and various International design centers.
Expanded my knowledge and experience with Cadence Place and Route tools.

ADDITIONAL EXPERIENCE:
MCC - Austin, TX [1999 - 2000]
Somerset Design Center - Austin, TX [1992 - 1999]
Actel Corporation - Sunnyvale, CA [1991 - 1992]
AMD - Sunnyvale, CA/ Austin, TX [7 years]
Teledyne Semiconductor - Mt. View, CA
Signetics Corporation - Sunnyvale, CA
Fairchild Corporation - Mt. View, CA
National Semiconductor - Santa Clara, CA

EDUCATION:
Intel Training - STX tool, Tridia VNC
ACC - QBASIC Programming Language
Cadence Training Center - Silicon Ensemble, Virtuoso Custom Router
Motorola University - Unix 101,102
California Academy of Drafting - Electro Mechanical Drafting, MOS Design.

Layout, Mask Design, Verification, Place and Route, Floor Planning, RFIC, Mixed Signal, CMOS, BiCMOS, Analog, Digital, Memory, Cache