Rigel: 1000-core Computing for the Masses
Event: Computer Architecture Seminar Series
Speaker: Sanjay Patel, University of Illinois at Urbana/Champaign
Title: "Rigel: 1000-core Computing for the Masses"
Date: Thursday, September 18, 2008 **Note different day**
Time: 3:30 pm
Place: ACES 2.302 **note different room**
Coffee: 3:00 pm
Host: Steve Keckler
Abstract:
Consumer-side computing is again exerting its forces on the
computing industry. Video gaming, diverse media, high-definition
video content have created a deep consumer demand for higher
performance, and have brought supercomputing to the masses. Game
consoles and graphics chips today have performance levels that have
broken the TFLOPs barrier, with chip architectures that boldly
embrace parallelism with 100s of cores. High-performance, parallel
computing has entered our living room.
This democratization of high-performance computing is creating a
transformational environment for many applications domain, which are
seeing new capabilities enabled by these increases in performance.
Rigel is a project are embarking on at Illinois where we are
developing a 1000+ core architecture capable of scaling beyond 10
TFLOPs. We are using the Rigel chip as a development catalyst and
for parallel programming frameworks for the masses and for next-
generation visual computing applications. Rigel espouses a massive
MIMD, scalable incoherent shared memory model, with a simple on-chip
interconnect In this talk I will provide an overview of the
project, technical rationale for the architecture, and some details
on the low-level parallel programming model.