Software Engineer supporting chip design and verification

Worked as a Software Engineer for a global leader in the design and manufacture of embedded semiconductors:
* Successfully led a cross-functional team of design and verification engineers, debugger developers, and applications engineers to design a C API for run control and access of architected features (registers, memory, caches) on PowerPC microprocessors/SoCs. Implemented and delivered API libraries for several targets, resulting in considerable time and cost savings for debugger developers.
* Developed a C++ JTAG driver reused in several testbench environments for simulation and emulation. Driver enabled 200X faster access of scan chains during simulation at a low cost per project.
* Enhanced and provided extensive user support for a C++ library allowing engineers to easily build a verification environment/testbench.
* Other work: biased random instruction level test generator for PowerPC cores; Java tool used to access registers, arrays, scan chains, and memories of cores/SoCs through their JTAG ports; tool used to process instruction level tests to run on silicon.

Other experience:
- Scientific/Applications programmer
- AIX/ESA Kernel I/O programmer: I/O subsystem, device drivers, hardware error recovery, user-level commands