Your thoughts, insights, experiences
and comments on transistioning from being
a Functional Verification Engr to being
Post-Silicon validation person in the lab?.
Of course, you'll lose the ability to directly see inside the logic. And in cycle-accurate simulations during functional verification, you don't have to worry about those pesky intra-cycle timings. Whereas during test & validation, you'll be working with "real" signals on the I/O's, where setup & hold times must be adhered to.
I believe your verification experience will certainly come in handy. For example, since you have likely spent time looking at RTL to diagnose issues during verification, you have an intrinsic idea about what logic looks like behind I/O's; I think an intuition stemming from that background will kick in during debug. In addition, you can better deal with test pattern issues because you already have experience generating them from the verification side.
Personally, I liked working on the testers when I was in Product & Test Engineering. My favorite task was designing matrix lots and subsequent characterization so we could get an idea of how much performance (within reason) could be squeezed out of the devices.
Submitted by ljsmiers on Sat, Aug 11 2007 - 12:37 PM.
Leslie Smiers
I agree with Matt that your verification experience will be very helpful in doing post silicon validation. I have had a designer tell me that validation people are mostly programers that write drivers, but have no clue when something goes wrong. This is one area were experience with c and C++ is a very big plus.
One thing to think about is do you consider yourself a "real world" person or a "virtual world" person or both? Validation is the "real world" so it can get complicated and frustrating. Some people like the satisfaction of seeing silicon work or solving complicated problems.
BTW, I thing Intel needs validation engineers. I have gotten several calls from them looking for a validation person.
Submitted by rkumar on Mon, Sep 3 2007 - 10:52 AM.
Yes I think couple of months back, some recuriter called for "validation" position at Intel and it was Pre-Si there. I guess they call Post-Si as Test
Engrs from what I heard. In most other
"big" companies, Validation is always
default Post-Si!. Just confirming
Maria's comments! :)
Submitted by ljsmiers on Wed, Sep 5 2007 - 11:38 AM.
Leslie Smiers
I had phone interviews with several Intel validation groups and almost all were pre and post Si. One group was creating tester patterns which I consider post Si. I think the meaning of jobs can range greatly inside a big company like Intel. Also I noticed some of the groups consider verification and validation as meaning same thing.
Submitted by FredB on Wed, May 21 2008 - 10:39 PM.
Hi, new to this group. This topic is near and dear to me. Pre-Si verification experience is a big definite plus for post si validation test development and root cause debug efforts. The closer the design/verif and validation test dev and debug teams are tied, the more effect post si work is. That can not be stressed enough.
FredB
Submitted by nzook on Tue, May 27 2008 - 11:05 AM.
I would caution on this. Post-Si validation (my expertise) is very much a software role, pre-Si verification is hardware. A good validator is first a good programmer. Even major companies fail to understand how important this distinction is. I took a piece of code which required six months for minor ports, and got it down to one month for major ports. How? The original code was written by hardware guys.
Do the validation and verification teams need to be intimate? Absolutely. Can the team members move back and forth? Very rarely.
Oh, and I consider cycle-for-cycle reproducibility in hardware to be a requirement for validation.
Comments
Well... there's the loss of
Well... there's the loss of that internal chip visibility we know and love.
Of course, you'll lose the
Of course, you'll lose the ability to directly see inside the logic. And in cycle-accurate simulations during functional verification, you don't have to worry about those pesky intra-cycle timings. Whereas during test & validation, you'll be working with "real" signals on the I/O's, where setup & hold times must be adhered to.
I believe your verification experience will certainly come in handy. For example, since you have likely spent time looking at RTL to diagnose issues during verification, you have an intrinsic idea about what logic looks like behind I/O's; I think an intuition stemming from that background will kick in during debug. In addition, you can better deal with test pattern issues because you already have experience generating them from the verification side.
Personally, I liked working on the testers when I was in Product & Test Engineering. My favorite task was designing matrix lots and subsequent characterization so we could get an idea of how much performance (within reason) could be squeezed out of the devices.
In other words, fun with shmoos.
Best of luck to you. Cheers,
Matt
--
Maria and Matt, Thanks for
Maria and Matt,
Thanks for your reply and comments!..
If anybody out there need to add some
more, Pl. feel free to!.
-Regards
Kumar.
Leslie Smiers I agree with
Leslie Smiers
I agree with Matt that your verification experience will be very helpful in doing post silicon validation. I have had a designer tell me that validation people are mostly programers that write drivers, but have no clue when something goes wrong. This is one area were experience with c and C++ is a very big plus.
One thing to think about is do you consider yourself a "real world" person or a "virtual world" person or both? Validation is the "real world" so it can get complicated and frustrating. Some people like the satisfaction of seeing silicon work or solving complicated problems.
BTW, I thing Intel needs validation engineers. I have gotten several calls from them looking for a validation person.
At least in the group that I
At least in the group that I interviewed with, Intel's definition of "validation" is pre-Si functional verification and DFT.
Yes I think couple of months
Yes I think couple of months back, some recuriter called for "validation" position at Intel and it was Pre-Si there. I guess they call Post-Si as Test
Engrs from what I heard. In most other
"big" companies, Validation is always
default Post-Si!. Just confirming
Maria's comments! :)
-RK
Yes, I thought it was only
Yes, I thought it was only Intel that flip-flopped the two. So Kumar, let us know how the new "post-silicon" position is going when you get a chance!
Matt
--
Leslie Smiers I had phone
Leslie Smiers
I had phone interviews with several Intel validation groups and almost all were pre and post Si. One group was creating tester patterns which I consider post Si. I think the meaning of jobs can range greatly inside a big company like Intel. Also I noticed some of the groups consider verification and validation as meaning same thing.
Hi, new to this group. This
Hi, new to this group. This topic is near and dear to me. Pre-Si verification experience is a big definite plus for post si validation test development and root cause debug efforts. The closer the design/verif and validation test dev and debug teams are tied, the more effect post si work is. That can not be stressed enough.
FredB
I would caution on this.
I would caution on this. Post-Si validation (my expertise) is very much a software role, pre-Si verification is hardware. A good validator is first a good programmer. Even major companies fail to understand how important this distinction is. I took a piece of code which required six months for minor ports, and got it down to one month for major ports. How? The original code was written by hardware guys.
Do the validation and verification teams need to be intimate? Absolutely. Can the team members move back and forth? Very rarely.
Oh, and I consider cycle-for-cycle reproducibility in hardware to be a requirement for validation.