SoC Design / Integration Engineer

SUMMARY

Highly motivated, results-oriented, electrical engineer experienced in high-speed digital circuit
design using CMOS SOI/bulk technologies, high-speed memory design (SRAM), low-power design, and mixed-signal circuit design. Experienced in all phases of ASIC design including synthesis, timing closure, and place and route using tool suites from Magma and Cadence.

PROFESSIONAL EXPERIENCE

Freescale Semiconductor, Austin TX 2006 -2009
Senior Design Engineer

* Developed procedures to evaluate the routability of internal and externally available libraries at the 45 / 65 / 90 nM nodes. Cells identified by these procedures were then modified, and resulted in reductions in die size and cycle time.

* Identified circuit design and routability issues for the 32 nM SOI cell library being developed in conjunction with IBM, allowing rapid evaluation of DRM changes.

* Provided integration support for all design teams, and developed back-end flows allowing existing designs to take advantage of library enhancements to reduce die size.

Magma Design Automation, Dallas TX 2005 - 2006
Senior Applications Engineer

* Developed physical design flow with Texas Instruments Wireless Design center for their
45/65 nM designs using Magma 5.0 (Talus). Designs included multi-VDD domains, state-retention circuitry, and low-leakage architectures for wireless applications. This development work allowed TI to reduce their die size, and design cycle time.

Vitesse Semiconductor, Dallas TX 2002 - 2005
Design Manager / Senior Digital Design Engineer

* Design manager of a group responsible for the design and development of 5-10 million gate
mixed signal ASICs in TSMC's 0.13 uM CMOS technology. Performed simulation, floor planning, place and route, verification, top-level mixed signal macro integration, and all static timing closure.

* Designed digital circuit blocks, and completed verification, silicon bring-up, and lab validation of high-speed physical layer interface devices.