Senior Digital IC Design and Physical Synthesis Engineer

Objective
*To obtain a challenging hardware logic design position, which utilizes and increases my current skill set leading to first-pass functional silicon.

Skills
*Verilog RTL design, Low Power coding practices, Full chip integration, synthesis, constraint development and STA, Verification and Logical Equivalence Checking
*Tools: Cadence RC, Magma, Synopsys DC, Synopsys PrimeTime, Modelsim, Verilog-XL, NCVerilog, NCSim, VCS, Conformal-LEC/ECO/Lint, Novas Debussy/Verdi, Leda, SVN, CVS and ClearCase
*Languages: Verilog, VHDL, Tcl, C, Perl, XML, Power PC assembly and DSP56300 assembly

Work Experience
5/2008 – 2/2009 Freescale – MAD Division (Formerly Sigmatel) Austin, TX
Senior IC Design Engineer
i.MX38 – Mixed Signal ARM1176JZFS based 720P Video and Graphics Applications Processor
* Enhanced reusable synthesis flow to handle 90nm mixed 7 and 12 track implementation, mixed language (VHDL and Verilog) designs, latest Cadence RC 8.2 version improvements for LEC and
DFT, and RC logfile parsing. Responsible for writing constraints, STA, fixing DFT issues, increasing
scan coverage.
* Synthesis responsibilities included very large hard-macro blocks such as ARM1176JZFS+ETM CPU, UTMI USB interface, Imagination Technologies SGX520 (mixed language 2D/3D graphics core), Chips&Media VPU (HD video codec), and ring oscillator. Also responsible for top-level synthesis of the i.MX38 SoC.
* Responsible for design of the clock control block. This block is designed in a rigorous and methodical manner to control the DFT and functional system asynchronous reset, 80 internal and system
asynchronous clock domains, root level clock gating, AC scan control, and DFT clock muxing to avoid clock reconvergence across the entire SoC. This clock control implementation improved upon the
previous design by allowing for multiple scan and AC scan clock domains for better test coverage and to relieve voltage IR drop concerns. Clock control “synthesis testbench” was created to develop chip level clock constraints in a time efficient manner for reuse in the full SoC.
* Redesigned the UTMI module’s clock control block to be consistent with the SoC clock control power up and design methodology.
* Worked closely with thephysical implementation and architecture teams to help drive initial floor planning, hard macro implementation flow and solve timing closure issues between FE and RC.
* Implemented reusable Cadence LEC lint checking scripts for the design team to verify their blocks. This allowed reduction in chip-level synthesis iterations by increasing the quality of inputs into the flow.

6/2006 – 5/2008 Sigmatel – PSG Division Austin, TX
Senior IC Design Engineer
STMP3780 – Mixed Signal ARM926 based MP3/Video Multimedia Processor – This SoC was fully functional on first tapeout and is currently being designed into PMP products by key customers.
* Implemented a consistent and highly reusable synthesis flow with Cadence RC. The flow is capable of reading in any combination of verilog RTL, netlist or lib files. Responsible for writing constraints, STA, fixing DFT issues and synthesis for the following modules the ARM926JZFS, UTMI USB interface, and the full top-level STMP3780 SoC. Generic constraints were written in a manner to work across
multiple tools including Cadence RC, Cadence FE and Synopsys PrimeTime. This removed the need to read in SDC constraints into FE and Primetime.
* Responsible for design of the STMP3780 clock control block with 60 internal and system asynchronous clock domains. One of the highlights of this clock control module is the ability to switch
between an asynchronous CPU/AHB Bus and EMI clock domains to a fully synchronous CPU/AHB Bus/EMI clock domains where the synchronous CPU/AHB frequency can be changed independently
from the EMI frequency for reduced system latency.
* Maintained and implemented bug fixes for the I2C block.
* Lint Checked the STMP3780 with Synopsys Leda.

STMP37x0 – Mixed Signal ARM926 based MP3/Video Multimedia Processor. This SoC was fully functional on first tapeout and is designed into products such as the Creative Zen X-Fi.
* Took ownership of existing I2C protocol block and verified with SoC verilog testbench.
* Lint Checked the STMP37x0 chips with Synopsys Leda and parsed output to design web page for block owner review.
* Retargeted ARM926 validation environment to be compatible with Sigmatel’s design flow. This was used as a silicon signoff metric.
* Used Cadence LEC-ECO to identify potential gate fix for the USB block in the tapeout netlist.

8/2004 – 6/2006 Freescale – IMTD Division Austin, TX
Senior IC Design Engineer
MPC5121E - Power PC based Telematics Processor
* Implemented fully synthesizable DQS PHY for integration with an external memory controller. The design utilized clock gating for low power applications. The DQS PHY supports mobile-DDR, DDR
and DDRII external memories.

MPC5222 - Power PC based Telematics Processor
* IMTD-Austin verification team leader. Responsible for bringing the Vera verification environment online within the ClearCase network. Organized training and coordinated block and integration verification effort with the verification team lead in Munich, Germany.
* Designed an internal SRAM controller cross bar switch. The design was configurable to support any number of master ports and SRAM banks. All master’s requests would be serviced simultaneously as
long as there was not an arbitration conflict for the same SRAM bank.
* Performed lint checking, LEC, synthesis, STA and ATPG for the SRAM controller.
* Verified design with a Verilog unit testbench, and Vera unit and SoC testbench.

MPC5200B - Power PC based Telematics Processor – This SoC was designed into products such as GM’s OnStar.
* Designed fully synthesizable and DFT capable PHY to delay the clock (SDR) and DQS strobe (DDR)
¼ memory clock period for read data recovery.
* Performed preliminary synthesis to determine feasibility of the design concept for the PHY.
* Removed the original delay chain logic, and integrated the new PHY with the existing SDRAM (SDR/DDR) memory controller in the MPC5200 SoC.
* Assisted with design modifications to add 16-bit external memory interface capability to the SDRAM memory controller.
* Verified the PHY and SDRAM memory controller with the existing unit level and SoC testbench platforms for RTL and gate netlist with back annotated timing.
* Assisted with synthesis and backend timing closure of SDRAM memory controller.
* Lab evaluation of PHY and SDRAM memory controller.
* Implemented ECO fixes for PHY and SDRAM memory controller. Used LEC and functional verification to verify design fixes.
* Developed test patterns for qualification and product test.

10/2000 – 8/2004 Motorola – DART Division Austin, TX
Senior IC Design Engineer
DSP56374 - Audio Processor – This SoC was fully functional on first tapeout and designed into products such as the Bose Wave Radio.
* Designed fully synthesizable and DFT capable frequency lock detect to fix a performance issue with the DSP56371. This design was integrated with a TSMC 0.13 PLL.
* Interface with Analog Design team to model PLL characteristics, and test frequency lock detect in MCSpice.
* Developed the unit testbench, and verified the frequency lock detect module at the unit and SoC levels for RTL and gate netlist with back annotated timing.
* Preliminary synthesis of the frequency lock detect for unit level verification.
* Assisted with backend timing closure.
* Updated the existing DSP56371 testbench environment for the DSP56374 development. Improved reusability of loading the test patterns into the DSP for future development.
* Integrated MJTAG Testbench (Motorola Proprietary JTAG Testbench) into the DSP56374 testbench environment. Used this testbench to integrate and debug the Boundary Scan and modify the JTAG
controller on the DSP56374.
* Developed test patterns for the frequency lock detect and Boundary Scan modules.

DSP56371 - Audio Processor
* Assisted with test pattern development and verification of the DSP56371.

MSDR540100FU – Digital IF Baseband Processor (DIF-BB) – This SoC was designed into Toyota automobiles such as the Camry and Prius.
* Created custom database infrastructure and repository management of IP between our four design centers: Austin, TX, Munich, Germany, Suzhou, China and Adelaide, Australia. Responsible for IP snapshots received from design centers, and SoC development releases to backend team.
* Verification responsibilities included setup and maintaining NCSim mixed Verilog/VHDL simulation environment for the design team. Assisting with development of SoC testbench. Integrating
companion DIF-IF SoC to verify LVDS protocol between the two devices. Regression testing before IP snapshot releases to backend team.
* Design responsibilities included integration of DSP56300 synthesizable core and 14 interface and coprocessor modules. Developed, implemented and verified the chip reset strategy and LVDS protocol for the DIF-BB. Developed, verified and synthesized FIR coprocessor used for up sampling in the radio data path. Implemented 27 ECO fixes to 14 different modules. Fixes were verified with LEC and functional patterns.

1/2000 – 10/2000 Motorola – NCSD Division Austin, TX
IC Design Engineer
Pluto – ADSL Copper Gold Rev2
* Designed a verilog, 100% efficient, FIR/IIR filter coprocessor that interfaced the embedded DSP56300 custom core.
* Responsibilities included design and synthesis of the coprocessor. Designing a VHDL unit testbench for verification of the coprocessor.

5/1999 – 7/1999 Motorola – CTASD Division Austin, TX
Summer Intern
* Designed a verilog SoC testbench, and developed functional tests to verify a high-speed codec (HSC).

Education
8/1994 – 12/1999 University of Nebraska-Lincoln Lincoln, NE
B.S. Electrical Engineering
GPA: 3.512