Design / Functional Verification

ahughes's picture

Sr. RTL design engineer

Experienced ASIC RTL designer responsible for architecting and implementing design IP products.

vruff's picture

Design Verification Engineer

SoC Design Verification Engineer

ASIC/FPGA design

Background information

Availability

Full-time (day)
Part-time (day)

Capacity

Employee
Consultant / Contractor

Hardware Design Engineer - EE

Background information

Result oriented electronics / IT industry professional with fourteen years of experience; three years in senior management of a startup company, preceded by four years in managing product development

Availability

Full-time (day)
Part-time (day)
Evenings
Weekends

Capacity

Executive / Board
Employee
Consultant / Contractor

Result oriented fellow, with one & half year of academic experience in Digital Integrated circuit design

Background information

Nishit Shah
712 SW 16th Avenue, Apt#215
Gainesville, FL-32601
(281) 678-4163
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EDUCATION:

Availability

Full-time (day)

Capacity

Employee