functional verification

Digital/Analog Logic Design

Background information

Cadence: IUS, Spectre
Synopsys: DC/DFT Compiler, Tetramax ATPG, Formality
Mentor: Modelsim
Altera: Quartus II
Xilinx: Xilinx ISE

Availability

Full-time (day)

Capacity

Employee

Software Engineer supporting chip design and verification

Background information

Worked as a Software Engineer for a global leader in the design and manufacture of embedded semiconductors:

Availability

Full-time (day)

Capacity

Employee
Consultant / Contractor