Verilog
Sr. Design and Verification Engineer
Background information
10 years ASIC design and Verification
15 years FPGA design and Verification
15 years PCB design and Verification
Availability
Capacity
Verification Engineer or Verification AE
Background information
DON TICARICH
2008 Dayflower Trace
Cedar Park, TX 78613
Email: dticarich@sbcglobal.net
Cell: 321-432-1535
Home: 512-250-1294
Career Objective
Availability
Capacity
Business Development Manager - ASIC
Background information
Assist customers with the selection of semiconductor components, including ASICs, FPGA, DSP, ASSP, Analog and Power, or Processor solutions that best suit their specifications.
Availability
Capacity
Verification
Background information
Good understanding of Simulators
Developing Verification Methodologies using HVLs
System Level Verification
HW/SW Co-Verification
Emulation and Acceleration Expertise
Availability
Capacity
Hardware Engineer/ CPU Architecture Designer
Background information
I am a PhD student and will be graduating this May 2008. I have interest as a hardware engineer. My academic research has focus on advance hardware algorithms for searching.