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» Design-For-Test
Design-For-Test
Digital Logic RTL Design Engineer
Communications
Design / Functional Verification
Logic Design
Synthesis & Timing
ASIC
design
Design-For-Test
DFT
FPGA
Logic
Mentor
ModelSim
Perl
RTL
SoC
SOC
Synopsys
Synthesis
Verification
Verilog
Background information
Availability
Full-time (day)
Capacity
Employee
