Senior Low Power Engineer
Over 10 years experience in design and verification at the block and chip level. Extensive work with Verilog, System Verilog, testbenches, Perl, and assembly languages.
Timothy J. Ehrler, PMP
7613 Jaborandi Dr., Austin, TX 78739
Phone: 512-382-6764 - Cell: 623-680-1551
10 years ASIC design and Verification
15 years FPGA design and Verification
15 years PCB design and Verification
Assist customers with the selection of semiconductor components, including ASICs, FPGA, DSP, ASSP, Analog and Power, or Processor solutions that best suit their specifications.
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