Synopsys

Chip Functional Verification

Background information

Over 10 years experience in design and verification at the block and chip level. Extensive work with Verilog, System Verilog, testbenches, Perl, and assembly languages.

Availability

Full-time (day)
Part-time (day)
Evenings
Weekends

Capacity

Employee
Consultant / Contractor

Sr. Design and Verification Engineer

Background information

10 years ASIC design and Verification
15 years FPGA design and Verification
15 years PCB design and Verification

Availability

Full-time (day)
Part-time (day)

Capacity

Employee
Consultant / Contractor

Business Development Manager - ASIC

Background information

Assist customers with the selection of semiconductor components, including ASICs, FPGA, DSP, ASSP, Analog and Power, or Processor solutions that best suit their specifications.

Availability

Capacity