Verification

Over 10 years experience in design and verification at the block and chip level. Extensive work with Verilog, System Verilog, testbenches, Perl, and assembly languages.

Objective
*To obtain a challenging hardware logic design position, which utilizes and increases my current skill set leading to first-pass functional silicon.

Skills

10 years ASIC design and Verification
15 years FPGA design and Verification
15 years PCB design and Verification