Verilog

ahughes's picture

Sr. RTL design engineer

Experienced ASIC RTL designer responsible for architecting and implementing design IP products.

SystemVerilog User Group Meeting

Oct 17 2007 2:00 pm
Oct 17 2007 6:00 pm

In addition to the presentations by industry experts during the user group meetings, we are also offering 2 tutorials. These tutorials will take place before the meeting in the same location and last about 90 minutes. Both start at the same time so you have to pick one or the other. They will be repeated at every SVUG meeting so if you don't have a chance to attend, there is always next time.